This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-61448 filed on Mar. 6, 2001; the entire contents of which are incorporated by reference herein.
The present invention relates to a semiconductor device having a contact electrode to a semiconductor substrate and its fabrication method, particularly to a highly integrated semiconductor device provided with a contact electrode close to an isolation region and its fabrication method.
Semiconductor devices are becoming increasingly highly densified. Because of the high densification of semiconductor devices, a method for forming an isolation region uses Shallow Trench Isolation (STI) method instead of local oxidation of silicon (LOCOS) method. In the case of the LOCOS method, the interval between metal oxide semiconductor (MOS) transistors increases. In the case of the STI method, a trench is formed in a semiconductor substrate and an insulating film is embedded in the trench. In the case of the STI method, it is possible to decrease the interval between MOS transistors depending on the interval between the trenches.
As shown in FIG. 1, an earlier semiconductor device has an isolation region 71 according to the STI method. A gate electrode 72 is formed on a semiconductor substrate 70 between the isolation regions 71. A source region 73 and a drain region 74 are formed nearby the surface of the semiconductor substrate 70 between the gate electrode 72 and the isolation region 71. The gate electrode 72 is formed on a gate oxide film 75 formed on the surface of the semiconductor substrate 70. The gate electrode 72 has an n+ type polycrystalline silicon layer 76, a stacked layer 77 of a tungsten (W) layer and a tungsten nitride (WN) layer, and a cap insulating film 78. A gate sidewall 79 is formed on the side face of the gate electrode 72. An interlayer dielectric film 80 is formed on the semiconductor substrate 70. Contact plugs 83 and 84 are formed in the interlayer dielectric film 80. A source contact plug 83 connects with a source region 73. A drain contact plug 84 connects with a drain region 74.
Distances X between the source contact plug 83 and the isolation region 71 is necessary. Distances X between the drain contact plug 84 and the isolation region 71 are necessary. An appropriate value for the distance X is decided by considering a misalignment value of a mask and dimensional fluctuations of a contact diameter. The distance X required is approximately 100 nm or more. Therefore, the distance X prevents a semiconductor device from becoming more highly densified.
If the distance X is not sufficient, the source contact plug 83 contacts with the isolation region 71 as shown in FIG. 2. In this case, the contact plug 83 may contact with the semiconductor substrate 70 below the source region 73. The semiconductor substrate 70 and the source region 73 would short-circuit. An MOS transistor would not operate normally. Short circuit failure may also occur in the drain region 74. Short circuit failure may also occur in both the source region 73 and drain region 74.
A semiconductor device according to embodiments of the present invention includes:
an isolation region which is embedded in a semiconductor substrate and isolates the surface of the semiconductor substrate and whose upper-face height is substantially equal to the height of the surface of the semiconductor substrate;
a semiconductor active region including the surface of the semiconductor substrate and formed below the surface;
a gate insulating film formed on the active region;
a gate electrode which is formed on the gate insulating film and set on or over the isolation region, whose first side face is set on or over the isolation region, whose second side face is set over the active region and crosses over the active region, and the entire surface of whose lower face is substantially flat;
a field insulator which is set on the isolation region, whose first side face contacts with a first side face of the gate electrode, and whose second side face is continuous with a face formed by extending a side face of the isolation region;
a sidewall insulator having a sidewall contacting with the second side face of the field insulator and the second side face of the gate electrode; and
a contact electrode set on the active region.